To debug an application, the debugger requires additional information to make the associations between the source code, the binaries generated from that original source and some other information. This information is included by default when the project is built using the "Debug" build configuration.
The SystemWorkbench debugger used is Arm GDB.
For the first time the user debug a program, a debug launch configuration must be created.
To create a debug configuration, use the following procedure:
- Within the Project Explorer, right-click on the project name and select Debug as > Debug Configurations.... from the menu.
- Double left-click on Ac6 STM32 Debugging to create a new Debug Configuration. Its name ("Multicore_Project Debug" in this example) and the path to the both executables are provided by the project.
- Click on the Main tab and make sure that the selected binary files and the project are the good ones.
- Click on the
button to select or unselect the binary file permits to the user to launch the debug on both cores or on only one.

- Click on the Debugger tab to see the GDB and the openOCD commands. If not relying on openOCD script Automated Generation, make sure that the Script File is the good one: It must contain the name of the board to use to debug the application.

- If relying on openOCD script Automated Generation, some advanced settings are available pushing Show generator options... button
- Connection Setup group is allowing to specify the debug probe communication channel and its clock speed.
- Note that SWD communication is always possible on all ST boards wheareas JTAG is only present on Evaluation boards.
- Note that SWD communication is always present on all Cortex-M devices whereas JTAG is not present on Cortex-M0(+) devices.
- Mode Setup group is allowing to setup Reset Mode and some others debug behaviors.
- Reset mode Connect under reset will assert Hardware Reset and then connect to the target (under reset).
- Reset mode Hardware reset will perform an Hardware Reset and then connect to the target.
- Reset mode Software system reset will not perform any Hardware Reset but will connect to the target and do a software system reset.
- Enable debug in low power modes will add some DBGMCU register writes to enable DBGMCU clock (uses more power).
- Stop watchdog counters when halt will add some DBGMCU register writes to freeze watchdog counters when core is halted.
- Refer to the Reference Manual of the device to know more about DBGMCU registers description.

- The Break Cross-Trigger Matrix allows to stop/run both cores simultaneously. By default it is not activated, that means that no core stops the other.

- Select the checkbox core CM7 breaks core CM4 means that if the core CM7 breaks, it will break the core CM4 but the core CM4 will not break the core CM7.
- Select the checkbox core CM4 breaks core CM7 means that if the core CM4 breaks, it will break the core CM7 but the core CM7 will not break the core CM4.
- Select the checkbox core CM7 breaks core CM4 and select the checkbox core CM4 breaks core CM7 means that whatever the core breaks, it will break the other.
The Break Cross-Trigger Matrix is also accessible during the debug when both cores are suspended:

- The ST-Link Server activation is done by enabling the checkbox “shareable ST-Link” and then select the board between all listed.

- Click on the Startup tab the initialization and the startup phases can be changed.
